Open Journal Systems

A detailed study on LDPC encoding techniques

V. Anand Kumar 1, Nandalal VIJAYAKUMAR 2

Article ID: 446
Vol 2, Issue 2, 2018, Article identifier:

VIEWS - 411 (Abstract) 298 (PDF)


This survey deals with LDPC encoding techniques. Different types of error detection and correction codes have been studied. BHC codes, Turbo code, LDPC Codes, Hamming codes are some of the vast classes of codes. Low Decoding complexity and efficient throughput are the achieved by using LDPC codes. Robert G.Gallager introduced this code so LDPC codes are Gallager code. After then Mackay and Neal in 1995 rediscovered LDPC codes because of its bit error performance. It consist of sparse of ones ie., low density of one’s because of this property decoding is simple. The major setback in LDPC codes are Encoding Complexity. WLAN (IEEE 802.11n) and MIMO OFDM are some of the applications of code. This code is a class of forward error correction (FEC) technique that exhibits capacity of impending near Shannon’s limit. LDPC codes are well identified for their capacity-approaching performance The LDPC codes have been selected as forward error correction in application including digital video broadcasting (DVBS2), 10 Gigabit Ethernet (10GBASE-T) broadband wireless access (Wi-Max), wireless local area network, deep-space communications.



Full Text:


Included Database


Bocharova IE, Kudryashov BD, Johannesson R. Searching for binary and non-binary block and convolutional LDPC codes. IEEE Transaction 2015.

Genga Y, Olayinka O, Olutayo O, et al. A low complexity encoder construction for systematic quasi-cyclic LDPC codes. IEEE African 2017 Proceedings 2017; 9: 167-170.

Yi HC, Jue HH, Zong YS. Wi-Fi LDPC encoder with approximate lower triangular diverse implementation and verification. IEEE Transaction 2014; 2.

Chen D, Chen P and Fang Y. Low-complexity high-performance low-density parity-check encoder design for china digital radio standard. IEEE Transaction 2017.

Nelson AF, Joaquim RS, Wagner LA, et al. VLSI architecture design and implementation of a ldpc encoder for the ieee 802.22 wran standard. IEEE Transaction 2015: 71-76.

Jayashree CN, Siddarama RP. Flexible hardware architecture for LDPC encoder. IEEE Transaction 2016.

Chen YH, Hsiao J, He JS. FPGA implementation of ldpc encoder with approximate lower triangular matrix. IEEE Transaction 2012: 158-162.

Steffy J, Nidhi G. Comparison of FPGA implementation of LDPC encoder algorithms. IEEE Transaction 2016: 603-606.

Sandeep K, Atish K. VLSI implementation of a rate decoder for structural LDPC channel codes. Elsevier 2016; 79: 765 – 771.

Arijit D, Ankita P. Modified approximate lower triangular encoding of LDPC codes. IEEE Transaction 2015; 3: 364 – 369.

Chetna NK, Jadhav MM, Sapkal AM. FPGA Implementation of linear LDPC encoder. International Journal of Research in Engineering and Technology 2013; 2(11): 441-447.

(411 Abstract Views, 298 PDF Downloads)


  • There are currently no refbacks.

Copyright (c) 2018 Wireless Communication Technology

Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.